The present invention refers to a device and a method for programming nonvolatile memory cells with automatic generation of the programming voltage.
As is known, programming of nonvolatile memory cells, for example of the flash or EEPROM types, is based upon injection of hot electrons, according to which sufficiently energetic electrons are trapped in the floating gate region of the memory cell to be programmed.
For this purpose, between the drain terminal and the source terminal of the cell to be written a high voltage is applied, so as to supply the electrons moving between these terminals with a sufficient energy to overcome the oxide potential gap. At the same time, by forcing on the gate terminal a potential higher than the drain terminal potential, an electric field is obtained that attracts the electrons towards the floating gate region through the oxide layer between the floating gate region and the channel region. The thus entrapped electrons modify of the threshold voltage of the cell.
Hot electron injection is, by its very nature, not controlled and not repeatable with precision. To obtain accurate programming of the cell, it is therefore necessary to use programming methods and/or control devices that enable interruption of the writing process when the desired threshold voltage value is reached.
For this purpose, many programming techniques of nonvolatile memory cells are known.
According to a first solution, programming is carried out by supplying the cell gate terminal with a number of programming pulses (write phase) and reading the threshold voltage after each pulse (verify phase). The programming process is stopped when the threshold voltage value read during verify is equal to the desired threshold voltage value.
The above solution, however, has the disadvantage that writing and verifying require distinct circuits and cannot be carried out at the same time. In addition, switching between write and verify configurations involves transients that must be exhausted before starting subsequent reading or writing. Consequently, the required programming times are long. In addition, the presence of different read and write circuits that the device has considerable overall dimensions. Furthermore, the write circuit must include devices for generating a ramp voltage necessary for biasing the control gate terminal. For this purpose, a digital-to-analog converter (DAC) is generally used, which, in turn, involves an increase in the required space.
A second solution (described in European Patent Application No. 97830477.2 dated Sep. 29, 1997) is based upon the circuit illustrated in FIG. 1. In this circuit, a memory cell 1, receiving at a gate terminal a voltage VG, has its drain terminal connected to a node 3 through a first bias transistor 2. The node 3 is connected to a current mirror circuit 4 comprising transistors 5 and 6. Transistor 6 is connected to an output transistor 7 through a second bias transistor 8. Bias transistors 2 and 8 have gate terminals connected together and to a bias voltage VB. An operational amplifier 9 has an inverting input connected to node 3, a non-inverting input connected to the drain terminal of transistor 6, and an output connected to the gate terminal of output transistor 7. The output voltage of the operational amplifier 9 is indicated by VO.
At the start of the programming phase, a high voltage VB (for example, 8 V) is supplied to the gate terminals of bias transistors 2 and 8, while a high voltage VG (for example, 12 V) is supplied to the gate terminal of cell 1 to be programmed. In these conditions, injection of hot electrons occurs in the floating gate region of cell 1, the threshold voltage of which increases. Consequently, the current If flowing in cell 1 decreases, whilst the potential of the node 3 increases. Under the effect of the operational amplifier 9, the voltage of the gate terminal of the output transistor 7 decreases, and hence also the current I7 flowing in transistor 7 decreases. During the programming phase, the currents If and I7 are not equal, but are, however, linked to each other. Therefore, the output voltage VO is, instant by instant, linearly dependent on the threshold voltage of cell 1, and for this reason gives a reading of the instantaneous value of the threshold voltage. The writing process is interrupted when the instantaneous value of the threshold voltage reaches the desired value.
In this case, a disadvantage is that the measurement of the instantaneous threshold voltage made through reading voltage VO is accurate and reliable only for medium-to-low values of the drain-to-source voltage of cell 1. Since the drain-to-source voltage increases during writing, the method described can be used only during an initial phase of the process; subsequently, it is necessary to resort to the traditional method, carrying out write and verify cycles to complete programming of the cell. Consequently, even though the write time is reduced, the presented solution involves a certain number of transients for switching between the write and verify configurations. In addition, a special write circuit is required for carrying out writing cycles, and thus the overall dimensions of the device remain larger then desired.
An embodiment of the invention is directed to an integrated memory device that includes a nonvolatile memory cell, a current mirror circuit, a negative feedback branch. The nonvolatile memory cell has first and second conduction terminals and a control terminal. The current mirror circuit has first and second nodes with the second node being coupled to the first conduction terminal of the memory cell. The negative feedback branch has first and second inputs and an output, the first and second inputs being connected to the first and second nodes, respectively, the output of the negative feedback means being connected to the control terminal of the memory cell. Such a current mirror and negative feedback branch provide an appropriate programming voltage to the memory cell during a programming phase and provide a drain voltage to the memory cell that is sufficiently low to prevent soft writing of the memory cell during a reading phase.